| 出版年月 |
著作類別 |
著作名稱 |
作者 |
收錄出處 |
| 2023-12 |
期刊論文
|
A 16nm 140TOPS/W 5µJ/inference keyword spotting engine based on 1D-BCNN |
Tay-Jyi Lin, Yi-Hsuan Ting, Meng-Ze Hsu, Kuan-Han Lin, Chung-Ming Huang, Fu-Cheng Tsai, Shyh-Shyuan Sheu, Shih-Chieh Chang, Chingwei Yeh, and Jinn-Shyan Wang |
IEEE Transactions on Circuits and Systems II: Express Briefs
|
| 2022-01 |
期刊論文
|
A low power fast switching write and standby shared assist circuit for low voltage SRAMs |
Jinn Shyan Wang*, Chien Tung Liu, Zhi Rong Liu, Shao Zhi Wang, and Jyun Jiea Kang |
Electronics Letters
|
| 2022-01 |
研討會論文
|
A 40nm CMOS SoC for real-time dysarthria voice conversion of stroke patients |
Tay-Jyi Lin, Chen-Zong Liao, You-Jia Hu, Wei-Cheng Hsu, Zheng-Xian Wu, Shao-Yu Wang, Chun-Ming Huang, Ying-Hui Lai, Chingwei Yeh, and Jinn-Shyan Wang* |
|
| 2020-10 |
研討會論文
|
A 0.21V 40nm NAND-ROM for IoT sensing systems with long standby periods |
Jinn-Shyan Wang*, Cheng-Xin Xue, and Chien-Tung Liu, and Tay-Jyi Lin |
|
| 2020-08 |
研討會論文
|
Low-active-energy and low-standby-power sub-threshold ROM for IoT edge sensing systems |
Jinn-Shyan Wang*, Chien-Tung Liu, and Chao-Hsiang Wang |
|
| 2020-06 |
期刊論文
|
A sub-mW on-chip period-jitter measurement circuit using automatic hidden run-time resolution calibration |
Pei-Yuan Chou, Yen-Chen Liu, Tay-Jyi Lin, Jim Wang, KC Wu, and Jinn-Shyan Wang |
IEEE J. Solid-State Circuits Letter
|
| 2020-01 |
研討會論文
|
A 0.23V 40nm OAI-ROM with low active and standby power for AI-based IoT edge devices |
Jinn-Shyan Wang*, Cheng-Xin Xue, and Chien-Tung Liu, and Tay-Jyi Lin |
|
| 2019-03 |
期刊論文
|
An all-digital on-chip peak-to-peak jitter sensor with automatic resolution calibration for high PVT-variation resilience |
Pei-Yuan Chou and Jinn-Shyan Wang |
IEEE Transactions on Circuits and Systems I: Regular Papers
|
| 2018-10 |
研討會論文
|
A low-power high-resolution all-digital on-chip jitter sensor for A 1-3 GHz clock generator |
Pei-Yuan Chou, Wei-Ling Lin, Chiang Hu Cheng, Tay-Jyi Lin, Jyh-Herng Wang and Jinn-Shyan Wang |
|
| 2018-09 |
研討會論文
|
A Low-Area, Low-Power, and Low-Leakage Error-Detecting Latch for Timing-Error Resilient System Designs |
Chien-Tung Liu, Zhe-Wei Chang, Shih-Nung Wei and Jinn-Shyan Wang |
|
| 2018-09 |
研討會論文
|
Near-Threshold CORDIC Design with Dynamic Circuitry for Long-Standby IoT Applications |
Pei-Yuan Chou, Ya-Bei Fang, Bo-Hao Chen, Chien-Tung Liu, Tay-Ji Lin and Jinn-Shyan Wang |
|
| 2018-08 |
期刊論文
|
A 0.2 V 32-Kb 10T SRAM With 41 nW Standby Power for IoT Applications |
Yung-Chen Chien and Jinn-Shyan Wang |
IEEE Transactions on Circuits and Systems I: Regular Papers
|
| 2018-05 |
研討會論文
|
Comparative study of sub-Vt SRAM bitcells based on noise-margin-aware design |
Yung-Chen Chien, Yi-Shiun Lin, Wei-Jia Weng, Chien-Tung Liu and Jinn-Shyan Wang |
|
| 2017-10 |
期刊論文
|
Process/Voltage/Temperature-variation-aware design and comparative study of transition-detector-based error-detecting latches for timing-error resilient pipelined systems |
Jinn-Shyan Wang and Shih-Nung Wei |
IEEE Trans. on VLSI Systems
|
| 2017-10 |
研討會論文
|
An all-N-type dynamic adder for ultra-low-leakage IoT devices |
Ya-Bei Fang, Pei-Yuan Chou, Bo-Hao Chen, Tay-Jyi Lin and Jinn-Shyan Wang |
|
| 2017-09 |
研討會論文
|
Approximate distributed arithmetic for variable-latency table lookup |
Yi-Hsuan Ting, Chih-Yang Wang, Yu-Sian Chang, Tay-Jyi Lin, Shih-Chieh Chang and Jinn-Shyan Wang |
|
| 2017-01 |
期刊論文
|
ULV-turbo cache for an instantaneous performance boost on asymmetric architectures |
Po-Hao Wang, Yung-Chen Chien, Shang-Jen Tsai, Xuan-Yu Lin, Rizal Tanjung, Yi-Sian Lin, Shu-Wei Syu, Tay-Jyi Lin, Jinn-Shyan Wang, and Tien-Fu Chen |
IEEE Trans. on VLSI Systems
|
| 2016-10 |
期刊論文
|
Zero-counting and adaptive-latency cache using a voltage-guardband breakthrough for energy-efficient operations |
Po-Hao Wang, Wei-Chung Cheng, Yung-Hui Yu, Tang-Chieh Kao, Chi-Lun Tsai, Pei-Yao Chang, Tay-Jyi Lin, Jinn-Shyan Wang, and Tien-Fu Chen |
IEEE Trans. Circuits and Systems II: Express Briefs
|
| 2016-10 |
研討會論文
|
A low-power low-cost built-in jitter measurement circuit for DDR4-2133 |
Pei-Yuan Chou, Wei-Ling Lin, Tay-Jyi Lin, Jyh-Herng Wang, and Jinn-Shyan Wang |
|
| 2016-09 |
研討會論文
|
Overoptimistic voltage scaling in pre-error AVS systems and learning-based alleviation |
Yi-Hsuan Ting, Chih-Yang Wang, Yu-Sian Chang, Tay-Jyi Lin, Shih-Chieh Chang, and Jinn-Shyan Wang |
|
| 2016-09 |
研討會論文
|
Variable-length VLIW encoding for code size reduction in embedded processors |
Ting-Yu Shyu, Bo-Yu Su, Tay-Jyi Lin, Chingwei Yeh, Tien-Fu Chen, and Jinn-Shyan Wang |
|
| 2016-08 |
研討會論文
|
Design of ultra-low-leakage near-threshold dynamic circuits in nano CMOS for IoT applications |
Bo-Hao Chen, Pei-Yuan Chou, Ya-Bei Fang, Ricky Lee, Tay-Jyi Lin, and Jinn-Shyan Wang* |
|
| 2016-02 |
期刊論文
|
Cross-matching caches: dynamic timing calibration and bit-level timing-failure-mask caches to reduce timing discrepancies with low voltage processors |
Po-Hao Wang, Shang-Jen Tsai, Rizal Tanjung, Tay-Jyi Lin, Jinn-Shyan Wang, Tien-Fu Chen |
Integration, the VLSI Journal
|
| 2016-01 |
研討會論文
|
Design of an all-digital temperature sensor in 28 nm CMOS using temperature-sensitivity-improved delay cells and adaptive-1P calibration for error reduction |
Shang-Yi Lee, Pei-Yuan Chou, and Jinn-Shyan Wang* |
|
| 2015-11 |
期刊論文
|
A wide-range, low-power, all-digital delay-locked loop with cyclic half-delay-line architecture |
Jinn-Shyan Wang*, Chun-Yuan Cheng, Pei-Yuan Chou, and Tzu-Yi Yang |
IEEE J. Solid-State Circuits
|
| 2015-11 |
研討會論文
|
Characterization of delay variations in modern FPGAs |
Chi-Hsuan Kao, Zih-Hong Yang, Cheng-Lan Huang, Yu-Sian Chang, Chung-Wei Wu, Ting-Yu Shyu, Pei-Yuan Chou, Tay-Jyi Lin and Jinn-Shyan Wang |
|
| 2015-11 |
研討會論文
|
Low-cost low-power droop-voltage-aware delay-fault-prevention designs for DVS caches |
Pei-Yuan Chou, I-Chen Wu, Jai-Wei Lin, Xuan-Yu Lin, Tien-Fu Chen, Tay-Jyi Lin, and Jinn-Shyan Wang |
|
| 2015-10 |
期刊論文
|
A calibration-free PVTD-variation-tolerant sensing scheme for footless-8T SRAM designs |
Jinn-Shyan Wang*, Yung-Chen Chien, Feng-Zhi Liu, and Pei-Yao Chang |
IEEE Trans. on Multi-Scale Computing Systems
|
| 2014-11 |
研討會論文
|
A 3 MHz-to-1.8 GHz 94 W-to-9.5 mW 0.0153-mm2 all-digital delay-locked loop in 65-nm CMOS. |
Jinn-Shyan Wang*, Chun-Yuan Cheng, Pei-Yuan Chou, Hsiu-Ching Chen, Chi-Tien Sun, and Yuan-Hua Chu |
|
| 2014-10 |
研討會論文
|
Operation-condition and timing-error collaborative monitoring for fixed-latency AVS designs |
Pei-Yuan Chou, Chung-Ling Liou, Jinn-Shyan Wang*, and Tay-Jyi Lin |
|
| 2014-09 |
期刊論文
|
Sub-threshold SRAM bit-cell PNN for VDDmin and power reduction in sub-threshold operations |
Y.C. Chien, I.H. Chiang and J.S. Wang |
Electronics Letters
|
| 2014-08 |
研討會論文
|
Low power fixed-latency DSP accelerator with autonomous minimum energy tracking (AMET |
Chung-Hsun Huang*, Keng-Jui Chang, Wei-Jen Chen, Yi-Hsuan Ting, Keng-Chang Hsu, Yu-Fu Pan, Chao-Chun Chen, Yuan-Hua Chu, Tay-Jyi Lin, and Jinn-Shyan Wang |
|
| 2014-06 |
研討會論文
|
Comparative analysis of flip-flops in sub- and near-threshold operations |
Jinn-Shyan Wang and Shih-Nung Wei |
|
| 2014-06 |
研討會論文
|
Technology migration study of digital CMOS temperature sensors |
Jinn-Shyan Wang, Zong-Wu He, Jen-Hsiang Lee, and Shang-Yi Lee |
|
| 2014-05 |
研討會論文
|
Accelerometer-based breathing signal acquisition with empirical mode decomposition |
Bo-Yuan Yang, Cheng-Chun Chang, Yi-Hsuan Ting, Jia-Wei Liao, Hong-Li Lin, Tay-Jyi Lin*, Chingwei Yeh, and Jinn-Shyan Wang |
|
| 2014-05 |
研討會論文
|
Adaptive variable-latency cache management for low-voltage caches |
Yung-Hui Yu, Po-Hao Wang, Tien-Fu Chen*, Tay-Jyi Lin, Jinn-Shyan Wang |
|
| 2013-10 |
研討會論文
|
Variation-aware and adaptive-latency accesses for reliable low voltage caches |
Po-Hao Wang*, Wei-Chung Cheng, Yung-Hui Yu, Tang-Chieh Kao, Chi-Lun Tsai, Pei-Yao Chang, Tay-Jyi Lin, Jinn-Shyan Wang, and Tien-Fu Chen |
|
| 2013-06 |
研討會論文
|
A 0.36V, 33.3μW 18-Band ANSI S1.11 1/3-Octave Filter Bank for Digital Aids in 40nm CMOS |
王進賢, Keng-Jui Chang1, 林泰吉, Richard Wu Prasojo, and 葉經緯 |
|
| 2013-03 |
期刊論文
|
Embedding Repeaters in Silicon Intellectual Properties for Cross-IP Interconnections |
Jinn-Shyan Wang, Keng-Jui Chang, Chingwei Yeh, and Shih-Chieh Chang |
IEEE Transactions on Very Large Scale Integration Systems
|
| 2013-02 |
研討會論文
|
A 0.48V 0.57nJ/pixel video recording SoC in 65nm CMOS |
Tay-Jyi Lin, Cheng-An Chien, Pei-Yao Chang, Ching-Wen Chen, Po-Hao Wang, Ting-Yu Shyu, Chien-Yung Chou, Shien-Chun Luo, Jiun-In Guo, Tien-Fu Chen, Gene C.H. Chuang, Yuan-Hua Chu, Liang-Chia Cheng, Hong-Men Su, Chewnpu Jou, Meikei Ieong, Cheng-Wen Wu, Jinn-Shyan Wang* |
|
| 2013-02 |
研討會論文
|
Self super cutoff power gating with state retention on a 0.3V 0.29fJ/cycle/gate 32-bit RISC core in 0.13um CMOS |
Jian-Shiun Chen, Chingwei Yeh, and Jinn-Shyan Wang |
|
| 2012-12 |
期刊論文
|
A 4R/2W Register File Design for UDVS
Microprocessors in 65-nm CMOS |
Pei-Yao Chang, 林泰吉, 王進賢, and Yen-Hsiang Yu |
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
|
| 2012-09 |
研討會論文
|
Design of a 2.5-GHz, 3-ps jitter, 8-locking- cycle, all-digital delay-locked loop with cycle-by-cycle phase adjustment |
Chun-Yuan Cheng, Jinn-Shyan Wang*, Cheng-Tai Yeh, and Jenn-Shyan Sheu |
|
| 2012-01 |
期刊論文
|
Design of 65nm sub-threshold SRAM using the bitline leakage prediction scheme and the non-trimmed sense amplifier |
Jinn-Shyan Wang, Pei-Yao Chang, and Chi-Chang Lin |
IEICE Trans. Electronics
|
| 2011-10 |
期刊論文
|
Towards process variation-aware power gating |
Chingwei Yeh*, Jinn-Shyan Wang |
IEEE Trans. VLSI
|
| 2011-10 |
研討會論文
|
RSCE-aware ultra-low-voltage 40-nm CMOS circuits |
Jinn-Shyan Wang*, Keng-Jui Chang, Shu-Yi Yang, Tsung-Han Hsieh, and Chingwei Yeh |
|
| 2011-08 |
期刊論文
|
A dynamic quality-adjustable H.264 Intra Coder,” IEEE Trans. Consumer Electronics |
Jia-Wei Chen, Hsiu-Cheng Chang, Jinn-Shyan Wang, and Jiun-In Guo |
IEEE Trans. Consumer Electronics
|
| 2011-07 |
期刊論文
|
Design of subthreshold SRAMs for energy-efficient quality-scalable video applications |
Jinn-Shyan Wang*, Pei-Yao Chang, Tai-Shin Tang, Jia-Wei Chen, and Jiun-In Guo |
IEEE J. on Emerging and Selected Topics in Circuits and Systems
|
| 2011-05 |
期刊論文
|
Design of high-performance CMOS level converters considering PVT variations |
Jinn-Shyan Wang*, Yu-Juey Chang, and Chingwei Yeh |
IEICE Trans. Electronics
|
| 2011-03 |
期刊論文
|
A scalable high-performance virus detection processor against large pattern set for embedded network security |
Chieh-Jen Cheng, Chao-Ching Wang, Wei-Chun Ku, Tien-Fu Chen*, and Jinn-Shyan Wang |
IEEE Trans. VLSI
|
| 2010-10 |
期刊論文
|
Heuristic Sizing Methodology to Design Energy-Efficient CMOS Level Converters with Balanced Rise and Fall Delays |
Jinn-Shyan Wang*, Yu-Juey Chang, and Chingwei Yeh |
IEICE Trans. on Electronics
|
| 2010-05 |
期刊論文
|
A duty-cycle-distortion-tolerant half-delay-line low-power fast-lock-in all-digital delay-locked loop |
Jinn-Shyan Wang*,Je-Ching Liu, Yu-Chia Liu, and Yi-Ming Wang |
IEEE J. Solid-State Circuits
|
| 2009-12 |
期刊論文
|
A dynamic quality-adjustable H.264 video encoder for power-aware video applications |
Hsiu-Cheng Chang, Jia-Wei Chen, Bing-Tsung Wu, Ching-Lung Su, Jinn-Shyan Wang, and Jiun-In Guo |
IEEE Trans. Circuits and Systems for Video Technology
|
| 2009-11 |
期刊論文
|
VisoMT: a collaborative multithreading multicore processor for multimedia applications with a fast data switching mechanism |
Wei-Chun Ku, Shu-Hsuan Chou, Jui-Chin Chu, Chi-Lin Liu, Tien-Fu Chen, Jiun-In Guo, and Jinn-Shyan Wang |
Trans. on Circuits and Systems for Video Technology
|
| 2009-11 |
研討會論文
|
A 439K Gates/10.9KB SRAM/2-328 mW Dual Mode Video Decoder Supporting Temporal/Spatial Scalable Video |
[4] Cheng-An Chien, Yao-Chang Yang, Jia-Wei Chen, Hsiu-Cheng Chang, Chin-Hsien Wang, Hsiang-Hui Huang, Ching-Hwa Cheng, Jinn-Shyan Wang, and Jiun-In Guo |
|
| 2009-05 |
期刊論文
|
An adaptively dividable dual-port BiTCAM for virus-detection processors in mobile devices |
Chao-Ching Wang, Chieh-Jen Cheng, Tien-Fu Chen, and Jinn-Shyan Wang |
J. Solid-State Circuits
|
| 2008-02 |
期刊論文
|
High-Speed and Low-Power Design Techniques for TCAM Macros |
王進賢*, Chao-Ching Wang and Chingwei Yeh |
IEEE J. of Solid-State Circuits
|
| 2008-02 |
研討會論文
|
An Adaptively Dividable Dual-Port BiTCAM for Virus-Detection Processors in Mobile Devices |
王進賢*, Chao-Ching Wang, Chieh-Jen Cheng, Tien-Fu Chen |
|
| 2007-11 |
研討會論文
|
A 0.67uW/MHz, 5ps Jitter, 4 Locking Cycles, 65nm ADDLL |
王進賢*, Chun-Yuan Cheng, Yu-Chia Liu, and Yi-Ming Wang |
|
| 2007-02 |
研討會論文
|
A 230mV-to-500mV 375KHz-to-16MHz 32b RISC Core in 0.18um CMOS |
王進賢*, 葉經緯, ...等 |
|
| 2007-02 |
研討會論文
|
A 7mW-to-183mW Dynamic Quality-Scalable H.264 Video Encoder Chip |
王進賢, 郭峻因, ...等 |
|
| 2007-01 |
期刊論文
|
A 160K Gates/4.5 KB SRAM H.264 Video Decoder for HDTV Applications |
王進賢, 郭峻因*, ...等 |
IEEE J. of Solid-State Circuits
|
| 2006-05 |
期刊論文
|
An AND-type match-line scheme for energy efficient content addressable memories |
[23] Hung-Yu Li, Chia-Cheng Chen, Jinn-Shyan Wang*, and Chingwei Yeh |
IEEE J. Solid-State Circuits
|
| 2006-05 |
研討會論文
|
Design of STR Level Converters for SOCs Using the Multi-Island Dual-VDD Design Technique |
王進賢, Yu-Juey Chang, Chingwei Yeh, and Yuan-Hua Chu |
|
| 2006-04 |
期刊論文
|
A high-performance direct 2-D transform coding IP design for MPEG-4 AVC/H.264 |
[22] Kuan-Hung Chen, Jiun-In Guo*, and Jinn-Shyan Wang |
IEEE Trans. Circuits and Systems for Video Technology
|
| 2006-02 |
研討會論文
|
A 160kGate 4.5kB SRAM H.264 Video Decoder for HDTV Applications |
C. C. Lin, J. I. Guo, H. C. Chang, Y. C. Yang, J. W. Chen, M. C. Tsai, 王進賢 |
|
| 2006-02 |
研討會論文
|
TCAM for IP-Address Lookup Using Tree-style AND-type Match Lines and Segmented Search Lines |
王進賢, Chao-Ching Wang, Chingwei Yeh |
|
| 2005-05 |
期刊論文
|
A power-aware IP core design for the variable-length DCT/IDCT targeting at MPEG4 shape-adaptive transforms |
王進賢, Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang, Ching-Wei Yeh, and Jia-Wei Chen |
IEEE Trans. Circuits and Systems for Video Technology
|
| 2005-05 |
期刊論文
|
Design Techniques for Single-Low-VDD CMOS Systems |
王進賢, Hung-Yu Li, Chingwei Yeh, and Tien-Fu Chen |
IEEE J. Solid-State Circuits
|
| 2005-02 |
研討會論文
|
An AND-type match-line scheme for energy-efficient content addressable memories |
王進賢, Hung-Yu Li, Chia-Cheng Chen, and Chingwei Yeh |
|
| 2005-02 |
研討會論文
|
An ultra low power, fast lock-in, small jitter, all digital delay locked loop |
王進賢, Yi-Ming Wang, Chin-Hao Chen, and Yu-Chia Liu |
|
| 2004-08 |
研討會論文
|
Low-Power fixed-width array multipliers |
王進賢, Chien-Nan Kuo, and Tsung-Han Yang |
|
| 2004-07 |
研討會論文
|
A power-aware SRN-progressive DCT/IDCT IP core design for multimedia transform coding |
王進賢, [23] Kuan-Hung, Jiun-In Guo, and Chingwei Yeh |
|
| 2004-06 |
期刊論文
|
A low-power half-delay-line fast skew-compensation circuit |
王進賢, Yi-Ming Wang |
IEEE J. Solid-State Circuits
|
| 2004-05 |
研討會論文
|
A power-aware IP core design for the variable-length DCT/IDCT targeting at MPEG4 shape-adaptive transforms |
王進賢, [22] Kuan-Hung Chen, Jiun-In Guo, Ching-Wei Yeh, and Tien-Fu Chen |
|
| 2004-05 |
研討會論文
|
An All-Digital 50% Duty-Cycle Corrector |
王進賢, Yi-Ming Wang |
|
| 2004-05 |
研討會論文
|
Pseudo-Footless CMOS Domino Logic Circuits for High-Performance VLSI Designs |
王進賢, Shang-Jyh Shieh, Chingwei Yeh, and Yuan-Hsun Yeh |
|
| 2004-02 |
期刊論文
|
The CMOS Carry Forward Adders |
王進賢, Chung-Hsun Huang, Chingwei Yeh, and Chih-Jen Fang |
IEEE J. Solid-State Circuits
|
| 2003-02 |
期刊論文
|
High-performance and power-efficient CMOS comparators |
王進賢, Chung-Hsun Huang |
IEEE J. Solid-State Circuits
|
| 2003-01 |
期刊論文
|
Design theory and implementation for low-power segmented bus systems |
王進賢, W.B. Jone, H.I. Lu, I.P. Hsu, and J.Y. Chen |
ACM Trans. on Design Automation of Electronic Systems
|
| 2002-10 |
期刊論文
|
Low-Voltage Pulsewidth Control Loops for SOC Applications |
王進賢, Po-Huei Yang |
IEEE J. Solid-State Circuits
|
| 2002-01 |
期刊論文
|
Design of high-performance CMOS priority encoders and incrementer/decrementers using multi-level lookahead and multi-level folding techniques |
王進賢, Chung-Hsun Huang, and Yen-Chao Huang |
IEEE J. Solid-State Circuits
|
| 2001-10 |
期刊論文
|
Low-power and high-speed ROM modules for ASIC applications |
王進賢, Ching-Rong Chang and Cheng-Hui Yang, |
IEEE J. Solid-State Circuits
|
| 2001-08 |
期刊論文
|
Analysis and design of high-speed low-power CMOS PLA’s |
王進賢, Ching-Rong Chang, and Chingwei Yeh, |
IEEE J. Solid-State Circuits
|
| 2001-03 |
期刊論文
|
Low-voltage CMOS pulsewidth control loop using push-pull charge pump |
王進賢, Po-Huei Yang |
IEE Electronics Letters
|
| 2001-02 |
期刊論文
|
Charge Sharing Alleviation and Detection for CMOS Domino Circuits |
王進賢, Shih-Chieh Chang, Ching-Hwa Cheng, Wen-Ben Jone, Shen-Da Li |
IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems
|
| 2000-10 |
期刊論文
|
High-Speed and Low-Power Dynamic CMOS Priority Encoders |
王進賢, Chun-Hsing Huang |
IEEE J. Solid-State Circuits
|
| 2000-09 |
期刊論文
|
Low-speed scan testing of charge-sharing faults for CMOS Domino circuits |
王進賢, Ching-Hwa Cheng, Wen-Ben Jone, Shih-Chieh Chang |
IEE Electronics Letters
|
| 2000-04 |
期刊論文
|
Design of a 3-V 300-MHz low-power 8-b8-b pipelined multiplier using pulse-triggered TSPC flip-flops |
王進賢, Po-Huei Yang, and Duo Sheng |
IEEE J. Solid-State Circuits
|
| 2000-01 |
期刊論文
|
Low-power embedded SRAM with the current-mode write technique |
王進賢, Wayne Tseng, and Hung-Yu Li |
IEEE J. Solid-State Circuit
|
| 1999-03 |
期刊論文
|
Power-driven Technology Mapping Using Pattern-oriented Power Modeling |
王進賢, C. Yeh, C. C Chang |
IEE Proc.-Computers and Digital Tech.
|
| 1999-03 |
期刊論文
|
Segmented bus design for low-power system |
王進賢, J.Y. Chen, W.B. Jone, H.I. Lu, and T.F. Chen |
IEEE Trans. on VLSI Systems
|
| 1993-01 |
期刊論文
|
Analysis and design of a new race free four-phase CMOS logic |
王進賢, C. Y. Wu, K. S. Cheng |
IEEE J. Solid-State Circuits
|
| 1989-06 |
期刊論文
|
CMOS nonthreshold logic (NTL) and Cascode nonthreshold logic (CNTL) for high-speed application |
王進賢, C.Y. Wu, and M. K. Tsai |
IEEE J.Solid-State Circuits
|
| 1988-12 |
期刊論文
|
Low power dynamic ternary logic |
王進賢, C.Y. Wu, and M. K. Tsai |
IEE Proceedings G of Circuits, Devices and Systems
|
| 1987-02 |
期刊論文
|
The analysis and design of CMOS multidrain logic and stacked multidrain logic |
王進賢,C. Y. Wu and M. K. Tsai |
IEEE J.Solid-State Circuits
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技術移轉